1. Field of the Invention
The present invention relates to a magnetic random access memory or MRAM and a method for manufacturing such a memory.
2. Discussion of the Related Art
FIG. 1 illustrates the operation of a magnetic RAM. Such a memory comprises an array of memory elements arranged in rows and in columns, a single memory element 10 being shown in FIG. 1. Each memory element 10 is formed of the stacking of three layers: a first layer 12 formed of a magnetic material, for example, cobalt, having a fixed magnetic orientation, a second layer 14 formed of an insulator, and a third layer 16 formed of a ferromagnetic material, for example, a cobalt and iron alloy or a nickel and iron alloy, the magnetic orientation of which can vary. Insulating layer 12 behaves as a barrier to prevent the alloying between magnetic layer 12 and ferromagnetic layer 16 and to enable the passing of electrons, the spin of which must be maintained. Generally, each layer of the memory element may itself be formed of several layers. All the memory elements 10 of a same array column are connected to a conductive track 18, behaving as a bit line. A conductive track 20 is arranged above the memory elements 10 of a same array row but is not in electric contact with the memory elements of the row.
For each memory element 10 in the array, first layer 12 is connected via a portion 22 of connection to the drain (or to the source) of an N- or P-channel MOS transistor 24 having its source (or its drain) connected to a reference voltage, for example, ground GND. The gate of MOS transistor 24 is controlled by a gate control signal SG. The MOS transistor associated with each memory element may be replaced with a diode circuit. MOS transistor 24 has the function of selecting in read mode the memory element 10 to be addressed.
As an example, magnetic layer 12 of memory element 10 has a magnetic moment vector with a fixed orientation, whatever the amplitude of the magnetic field in which the memory element is bathed. Ferromagnetic layer 16 then has a magnetic moment vector with an orientation that can be modified by applying a magnetic field. As an example, binary data may be stored in the memory element by orienting the magnetic moment vector of ferromagnetic layer 16 in parallel or in antiparallel with respect to the magnetic moment vector of magnetic layer 12.
A data write operation into memory element 10 is performed by flowing a current through bit line 18 and bit line 20 associated with the memory element. The flowing of a current in bit line 18 causes the forming of a magnetic field having the general orientation of the field lines represented by arrow 26. Similarly, the flowing of a current in word line 20 causes the forming of a magnetic field having the general orientation of its field lines represented by arrow 28. According to the flow direction of the current in bit line 18 and word line 20, the magnetic moment vector of ferromagnetic layer 16 is oriented in parallel or in antiparallel with respect to the magnetic moment vector of magnetic layer 12. In a write operation, MOS transistor 24 is on.
An operation of reading of the binary data stored in memory element 10 is performed by turning off transistor 24 associated with memory element 10 and by flowing a current therein via bit line 18. The determination of the data stored in the memory element is based on the difference of the resistance of memory element 10 according to the orientation difference of the magnetic moment vectors of ferromagnetic layer 16 and of magnetic layer 12.
FIGS. 2A to 2G show successive steps of a conventional example of a method for manufacturing such a memory element 10 in integrated form. Such a method is especially described in U.S. Pat. No. 6,673,675, which is incorporated herein by reference.
As shown in FIG. 2A, the magnetic memory is formed on a substrate 30, for example, polysilicon, comprising insulation trenches 32 insulating the memory elements from one another. Two N-type doped regions 34, 36 form the source and drain regions of MOS transistor 24. The gate of MOS transistor 24 is formed of the stacking of a gate oxide layer 38, for example, silicon oxide, and of a gate layer 40, for example, polysilicon. Substrate 30 and the gate of MOS transistor 24 are covered with an insulating layer 42. A connection portion 44, for example, metallic, is buried at the surface of insulating layer 42 and is connected to doped region 36 via a contact 46. A connection portion 48, for example, metal, is buried at the surface of insulating layer 42 and is connected to doped region 34 via a via 50. Connection portion 48 is intended to be grounded. A conductive track 52, for example, metal, is buried at the surface of insulating layer 42 and forms word line 20.
FIG. 2B shows the structure obtained after having covered insulating layer 42 with an insulating layer 54, and having formed, in insulating layer 54, a connection portion 56, for example, metal, in contact with connection portion 44.
FIG. 2C shows the structure obtained after having covered insulating layer 54 with an insulating layer 58 and formed, in insulating layer 58, a connection portion 60, for example, metal, in contact with connection portion 56 and which extends substantially above word line 52.
FIG. 2D shows the structure obtained after having covered insulating layer 54 with an insulating layer 62 and etched a recess 64 with substantially straight sides in insulating layer 54, exposing a portion of connection portion 60.
FIG. 2E shows the structure obtained after having deposited, for example, by vapor phase deposition or cathode sputtering, on insulating layer 62, a magnetic layer 66, an insulating layer 68, a ferromagnetic layer 70, and a conductive layer 72, for example, metal. The deposited layers penetrate into recess 64 so that magnetic layer 66 is in contact with connection portion 60. Generally, magnetic layer 66 has a thickness of some ten nanometers, insulating layer 68 has a thickness of a few nanometers, and ferromagnetic layer 70 has a thickness of from some ten nanometers to a few tens of nanometers.
FIG. 2F shows the structure obtained after a chem./mech polishing (CMP) of layers 66, 68, 70, 72 down to insulating layer 62. A memory element 73 formed of the stacking of magnetic, insulating, and ferromagnetic portions 74, 75, and 76 is thus insulated. Portions 74, 75, 76 thus defined comprise corner areas 77, 78, 79. In other words, the resulting structure of memory element 73 after the planarization step has a “U”-shaped cross-section. Such corner areas 77, 78, 79 are undesirable since it is difficult to control the thickness of insulating portion 75 at the level of corner area 77. In particular, there is a risk for the thickness of insulating portion 75 to be locally decreased at the level of corner area 77. This may cause the occurrence of leakage currents between magnetic portion 74 and ferromagnetic portion 76, altering the operation of memory element 73. It is thus desirable to eliminate corner areas 77, 78, 79.
FIG. 2G shows the structure obtained after etching of corner areas 77, 78, 79 of memory element 73. A memory element 73 in which magnetic, insulating, and ferromagnetic portions 74, 75, and 76 are substantially planar is then obtained.
A disadvantage is that the materials generally used to form the memory elements are little reactive with chemical etches conventionally used in integrated circuit manufacturing processes, since there is no forming of volatile compounds. It is thus necessary to use RIE-type etches (reactive ion etching) to eliminate corner areas 77, 78, 79 from memory element 73. A disadvantage of such etchings is that the materials etched by an RIE-type etch tend to deposit back onto the walls of the etch chamber and/or onto other portions of the integrated circuit. This may result in a soiling of the etch chamber, and/or, which is much more disturbing, in the occurrence of defects at the integrated circuit level.